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Dinh Son T.

  

(Examiner)





Patents (300)

6F2 DRAM array with apparatus for stress testing an isolation gate and method
Adaptive precharge management for synchronous DRAM
Adaptive programming method and apparatus for flash memory analog storage
Address controlled sense amplifier overdrive timing for semiconductor memory device
Address transition detector (ATD) for power conservation
Address transition detector architecture for a high density flash memory device
Almost full, almost empty memory system
Antenna control system
Anti-fuse memory cell with asymmetric breakdown voltage
Antiferromagnetically coupled bi-layer sensor for magnetic random access memory
Antifuse method to repair columns in a prefetched output memory architecture
Apparatus and method for a one-phase write to a one-transistor memory cell array
Apparatus and method for address selection
Apparatus and method for programming PMOS memory cells
Apparatus and method for reducing leakage current in a dynamic random access memory
Apparatus and method for selectively configuring a memory device using a bi-stable relay
Apparatus and method for static random access memory array
Apparatus and methods for imprint reduction for ferroelectric memory cell
Apparatus for enabling EEPROM functionality using a flash memory device
Apparatus for feedback using a tunnel device
Apparatus for programming threshold voltage for non-volatile memory cell and method therefor
Apparatus for providing additional latency for synchronously accessed memory
Apparatus for providing additional latency for synchronously accessed memory
Apparatus for serial reading and writing of random access memory arrays
Architecture, method(s) and circuitry for low power memories
Arrangement comprising a memory device and a program-controlled unit
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
Array organization for high-performance memory devices
Associative memory
Associative memory, method for searching the same, network device, and network system
Auto-precharge during bank selection
Banked SRAM device with bit line refresh
Bi-level digit line architecture for high density DRAMS
Bi-level digit line architecture for high density drams
Bit line precharge circuit with reduced standby current
Bit line sensing circuit and method of a semiconductor memory device
Bit line sensing circuit of a semiconductor memory device
Bit refresh circuit for refreshing register bit values, integrated circuit device having the same, and method of refreshing register bit values
Bitline precharge circuit for semiconductor memory device
Block RAM with reset to user selected value
Block-writable content addressable memory device
Boosted sensing ground circuit
Boosted substrate/tub programming for flash memories
Boosted substrate/tub programming for flash memories
Buffer amplifier architecture for semiconductor memory circuits
Built-in self test for integrated circuits having read/write memory
Cache memory array which stores two-way set associative data
Card identification compatibility
Cell block structure of nonvolatile ferroelectric memory
Cell data margin test with dummy cell
Cell plate structure for a ferroelectric memory
Channel hot-carrier page write for NAND applications
Charge pump with large bypass capacitors
Charging a sense amplifier
Circuit and method for a high data transfer rate output driver
Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
Circuit and method for low voltage, current sense amplifier
Circuit calibrating output driving strength of DRAM and method thereof
Circuit configuration for driving a programmable link
Circuit configuration having a number of electronic circuit components
Circuit for driving nonvolatile ferroelectric memory
Circuit for programming antifuse bits
Circuit for reducing stand-by current induced by defects in memory array
Circuitry, apparatus and method for embedding quantifiable test results within a circuit being tested
Circuits, systems, and methods for re-mapping memory column redundancy
Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROM
Clock driver and boundary latch for a multi-port SRAM
Clock generator and method for generating a clock signal
Clock phase generator for controlling operation of a DRAM array
Cluster based redundancy scheme for semiconductor memories
Column redundancy of a multiple block memory architecture
Column redundancy scheme for serially programmable integrated circuits
Column select line control circuit for synchronous semiconductor memory device and associated methods
Combined digital write and analog rewrite process for non-volatile memory
Combined program and data nonvolatile memory with concurrent program-read/data write capability
Common-gate pre-driver for disc drive write circuit
Compact electrically erasable memory cells and arrays
Complementary differential amplifier in which direct current amplification gain can be set arbitrarily and semiconductor memory divice using the same
Configuration for data transmission in a semiconductor memory system, and relevant data transmission method
Content addressable memories
Content addressable memory architecture
Content addressable memory cell
Content addressable memory device
Content addressable memory device
Content addressable memory device for compensating faults
Content addressable memory system
Control circuit for an output driving stage of an integrated circuit
Control method of non-volatile semiconductor memory cell and non-volatile semiconductor memory device
Controlled temperature, thermal-assisted magnetic memory device
Controlling capacitive load
CPU capable of modifying built-in program codes thereof and method for the same
Current confined pass layer for magnetic elements utilizing spin-transfer and an MRAM device using such magnetic elements
Current steering reduced bitline voltage swing, sense amplifier
Current steering reduced bitline voltage swing, sense amplifier
Data holding circuit
Data output buffer control circuit of a synchronous semiconductor memory device
Data processing apparatus and memory card
Data processing apparatus having memory protection unit
Data signal distribution circuit for synchronous memory device
Data synchronization arrangement
Decode path gated low active power SRAM
Delay locked loop for use in synchronous dynamic random access memory
Delay locked loop monitor test mode
Device and method for stress testing a semiconduction memory
Device and method for stress testing a semiconductor memory
Device and method for the reading of EEPROM cells
Device for storing information and a method for partial write and restore
Device selection circuitry constructed with nanotube technology
Differential sensing in a memory with reference current
Digital multilevel memory system having multistage autozero sensing
Digital multilevel non-volatile memory system
Disabling clocked standby mode based on device temperature
Distributed programmed memory cells used as memory reference currents
Distribution of bank accesses in a multiple bank DRAM used as a data buffer
DLL circuit and a memory device building the same in
Double-high memory system compatible with termination schemes for single-high memory systems
DQS postamble filtering
Drain voltage pump circuit for nonvolatile memory device
DRAM sense amplifier having pre-charged transistor body nodes
DRAM sensing scheme for eliminating bit-line coupling noise
Driver circuit for semiconductor storage device and portable electronic apparatus
Driving circuit, charge/discharge circuit and the like
Dual mode memory with embedded ROM
Dual power sensing scheme for a memory device
Dual-port DRAM architecture system
Dual-port programmable logic device variable depth and width memory array
Dummy cell for providing a reference voltage in a memory array
Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
Dynamic memory cell for a programmable logic device
Dynamic random access memory with write-without-restore and systems and methods using the same
Dynamic random access memory word line boost technique employing a boost-on-writes policy
Dynamic semiconductor memory device
Dynamic semiconductor memory device superior in refresh characteristics
Dynamic semiconductor storage device and method of reading and writing operations thereof
Dynamic word line driver for cache
Early read after write operation memory device, system and method
EEPROM array using 2-bit non-volatile memory cells and method of implementing same
Electrically erasable and programmable nonvolatile semiconductor memory device having data holding function and data holding method
Electrically programmable resistance cross point memory sensing method
Electrically programmable semiconductor device with multi-level wordline voltages for programming multi-level threshold voltages
Electromechanical memory having cell selection circuitry constructed with nanotube technology
Enhanced bus turnaround integrated circuit dynamic random access memory device
Enhanced bus turnaround integrated circuit dynamic random access memory device
Entry relocation in a content addressable memory device
Erasing method in nonvolatile semiconductor memory device
Error detection and correction method and apparatus in a magnetoresistive random access memory
External compensation apparatus and method for fail bit dynamic random access memory
Fail number detecting circuit of flash memory
Failure tolerant memory device, in particular of the flash EEPROM type
Fast access memory array
Fast accessible non-volatile semiconductor memory device
Fast accessible non-volatile semiconductor memory device
Fast sense amplifier for small voltage differences
Fast-sensing amplifier for flash memory
FeRAM having wide page buffering function
Ferroelectric memory
Ferroelectric memory device
Ferroelectric random access memory devices having short-lived cell detector available for life test for ferroelectric capacitor and method for testing ferroelectric memory cells
Ferroelectric random-access memory
Ferroelectric storage device
FIFO configuration cell
FIFO unit with single pointer
Finite impulse response filter
Fixed-address digital data access system
Flash EEPROM Memory system for low voltage operation and method
Flash memory cell array and method for programming and erasing data using the same
Flash memory device
Flash memory device with a variable erase pulse
Flash memory device with a variable erase pulse
Flash memory device with improved pre-program function and method for controlling pre-program operation therein
Flash memory including improved transistor cells and a method of programming the memory
Flash memory system having fast erase operation
Flash memory system having fast erase operation
Flash memory system having fast erase operation
Flash memory with low tunnel barrier interpoly insulators
Flash/dynamic random access memory field programmable gate array
Flash/dynamic random access memory field programmable gate array
Flash/dynamic random access memory field programmable gate array
Floating wordline using a dynamic row decoder and bitline VDD precharge
Folded-bitline dual-port DRAM architecture system
Four device SRAM cell with single bitline
Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device
Fully-hidden refresh dynamic random access memory
Fuse circuit and semiconductor integrated circuit device
Fusleless memory repair system and method of operation
Giant magnetoresistive sensor, thin-film read/write head and magnetic recording apparatus using the sensor
Giant magnetoresistive sensor, thin-film read/write head and magnetic recording apparatus using the sensor
High density and speed magneto-electronic memory for use in computing system
High density magnetoresistance memory and manufacturing method thereof
High frequency memory module
High performance cost optimized memory with delayed memory writes
High speed analog flip-flop with embedded logic and phase-locked-loop circuit employing the same
High speed asynchronous and programmable state machine for generating almost empty synchronous flags in a synchronous FIFO
High speed data bus
High speed data bus
High speed data bus
High speed data bus
High speed data bus
High speed data bus
High speed data bus
High speed data bus
High speed I/O calibration using an input path and simplified logic
High speed memory interface
High speed semiconductor memory with burst mode
High voltage comparator
High voltage NMOS pass gate having supply range, area, and speed advantages
High-density non-volatile memory devices incorporating thiol-derivatized porphyrin trimers
High-speed and low-noise output buffer
High-speed read-write circuitry for semi-conductor memory
Hybrid circuit having nanotube electromechanical memory
Hybrid circuit having nanotube electromechanical memory
Hybrid magnetoresistive random access memory (MRAM) architecture
Identification and verification of a sector within a block of mass storage flash memory
Implementation of a multivibrator protected against current or voltage spikes
Information storage device, and information storage method and information regeneration method employing the information storage device
Integrated circuit device and method for applying different types of signals to internal circuit via one pin
Integrated circuit device and module with integrated circuits
Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory
Integrated circuit including sensor to sense environmental data, method of compensating an MRAM integrated circuit for the effects of an external magnetic field, MRAM integrated circuit, and method of testing
Integrated circuit memory device
Integrated circuit power management for reducing leakage current in circuit arrays and method therefor
Integrated circuit test systems that use direct current signals and impedance elements to improve test signal transmission speed and reduce test signal distortion
Integrated circuit with circuitry for overriding a defective configuration memory cell
Integrated circuit with improved output control signal and method for generating improved output control signal
Integrated DRAM with high speed interleaving
Integrated memory
Integrated semiconductor memory device for synchronizing a signal with a clock signal
Inter-row configurability of content addressable memory
Intermesh memory device
Internal clock generating circuit for clock synchronous type semiconductor memory device
Internal voltage generating circuit in semiconductor memory device
Isolation of memory cells in cross point arrays
Laser programmable electrically readable phase-change memory method and device
Latched row decoder for a random access memory
Leakage detection in flash memory cell
Local bit switch decode circuit and method
Logic and memory device integration
Low cost high density rectifier matrix memory
Low power content addressable memory architecture
Low power low area precharge technique for a content addressable memory
Low skew differential receiver with disable feature
Low-power static column redundancy scheme for semiconductor memories
LSI package and manufacturing method thereof
Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element
Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element
Magnetic element with an improved magnetoresistance ratio and fabricating method thereof
Magnetic element with dual magnetic states and fabrication method thereof
Magnetic logic elements
Magnetic memory and method for optimizing write current in a magnetic memory
Magnetic memory array, method for recording in a magnetic memory array and method for reading out from a magnetic memory array
Magnetic memory device
Magnetic memory devices having multiple magnetic tunnel junctions therein
Magnetic RAM cell device and array architecture
Magnetic random access memory
Magnetic random access memory
Magnetic random access memory using a non-linear memory element select mechanism
Magnetic storage device using unipole currents for selecting memory cells
Magnetic tunnel junctions using ferrimagnetic materials
Magneto-resistive device including clad conductor
Magnetoresistive device and magnetic memory using the same
Magnetoresistive effect element and magnetic memory having the same
Magnetoresistive effect element, magnetic memory device and method of fabricating the same
Magnetoresistive random access memory with reduced switching field
Magnitude comparator based content addressable memory for search and sorting
Main row decoder in a semiconductor memory device
Memories, systems, and methods using precision sense amplifiers
Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
Memory architecture with single-port cell and dual-port (read and write) functionality
Memory architecture with single-port cell and dual-port (read and write) functionality
Memory architecture with single-port cell and dual-port (read and write) functionality
Memory array architecture
Memory block select using multiple word lines to address a single memory cell row
Memory card
Memory card which is thermally controlled
Memory cell strings
Memory cell strings in a resistive cross point memory cell array
Memory cell that can store data nonvolatily using a ferroelectric capacitor, and a semiconductor memory device including such a memory cell
Memory circuit and method for sensing data
Memory circuit with auto redundancy
Memory circuit with switch for selectively connecting an I/O pad directly to a nonvolatile memory cell and method for operating same
Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell
Memory controller architecture
Memory data bus architecture and method of configuring multi-wide word memories
Memory device
Memory device
Memory device
Memory device
Memory device and method of operating same
Memory device for controlling programming setup time
Memory device having programmable column segmentation to increase flexibility in bit repair
Memory device redundancy selection having test inputs
Memory device testing
Memory device with pipelined column address path
Memory device, memory device read method
Memory embedded logic integrated circuit mounting memory circuits having different performances on the same chip
Memory having a synchronous controller and asynchronous array and method thereof



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