patentsmania.com
US patents database



Search:    

Information Technology / Static Information Storage And Retrieval / Testing


Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device

Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device

Multi-state EEprom read and write circuits and techniques

Multi-state EEprom read and write circuits and techniques

Multi-chip module testing

Multi-chip module testing

Semiconductor memory device capable of high speed plural parallel test, method of data writing therefor and parallel tester

Semiconductor memory device capable of high speed plural parallel test, method of data writing therefor and parallel tester

Semiconductor memory apparatus having refresh test circuit

Semiconductor memory apparatus having refresh test circuit

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Semiconductor integrated circuit and method for testing memory

Semiconductor integrated circuit and method for testing memory

Parallel tester capable of high speed plural parallel test

Parallel tester capable of high speed plural parallel test

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Semiconductor memory module

Semiconductor memory module

System and method for an antifuse bank

System and method for an antifuse bank

Dram with reduced-test-time mode

Dram with reduced-test-time mode

Forced substrate test mode for packaged integrated circuits

Forced substrate test mode for packaged integrated circuits

Integrated circuit having forced substrate test mode with improved substrate isolation

Integrated circuit having forced substrate test mode with improved substrate isolation

Integrated circuit memory devices having direct access mode test capability and methods of testing same

Integrated circuit memory devices having direct access mode test capability and methods of testing same

Circuit for SRAM test mode isolated bitline modulation

Circuit for SRAM test mode isolated bitline modulation

Apparatus and method for disabling and re-enabling access to IC test functions

Apparatus and method for disabling and re-enabling access to IC test functions

Integrated circuit having forced substrate test mode with improved substrate isolation

Integrated circuit having forced substrate test mode with improved substrate isolation

Redundancy analysis for embedded memories with built-in self test and built-in self repair

Redundancy analysis for embedded memories with built-in self test and built-in self repair

Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof

Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof

Integrated memory and method for testing and repairing the integrated memory

Integrated memory and method for testing and repairing the integrated memory

Electrically alterable nonvolatile semiconductor memory

Electrically alterable nonvolatile semiconductor memory

Programmable and electrically configurable latch timing circuit

Programmable and electrically configurable latch timing circuit

Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices

Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices

Test circuit for testing a circuit

Test circuit for testing a circuit

Synchronous semiconductor memory device capable of rapidly, highly precisely matching internal clock phase to external clock phase

Synchronous semiconductor memory device capable of rapidly, highly precisely matching internal clock phase to external clock phase

Selective application of voltages for testing storage cells in semiconductor memory arrangements

Selective application of voltages for testing storage cells in semiconductor memory arrangements

Method of measuring retention performance and imprint degradation of ferroelectric films

Method of measuring retention performance and imprint degradation of ferroelectric films

Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories

Method of evaluating the gate oxide of non-volatile EPROM, EEPROM and flash-EEPROM memories

Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays

Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays

Circuit and method of operating a ferrolectric memory in a DRAM mode

Circuit and method of operating a ferrolectric memory in a DRAM mode

Multi-state EEprom read and write circuits and techniques

Multi-state EEprom read and write circuits and techniques

Nonvolatile semiconductor memory device and manufacturing method and testing method thereof

Nonvolatile semiconductor memory device and manufacturing method and testing method thereof

Method and apparatus for verifying the programming of multi-level flash EEPROM memory

Method and apparatus for verifying the programming of multi-level flash EEPROM memory

Method for sorting semiconductor devices having a plurality of non-volatile memory cells

Method for sorting semiconductor devices having a plurality of non-volatile memory cells

High reliability triple redundant latch with voting logic on each storage node

High reliability triple redundant latch with voting logic on each storage node

Memory device and method of storing fail addresses of a memory cell

Memory device and method of storing fail addresses of a memory cell

Semiconductor memory device test apparatus

Semiconductor memory device test apparatus

Apparatus and method for testing a memory

Apparatus and method for testing a memory

Memory testing apparatus

Memory testing apparatus

Method and apparatus for testing embedded DRAM

Method and apparatus for testing embedded DRAM

Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory

Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory

Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same

Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same

Semiconductor memory device allowing spare memory cell to be tested efficiently

Semiconductor memory device allowing spare memory cell to be tested efficiently

Testing an integrated circuit device

Testing an integrated circuit device

Method for testing an on-chip cache for repair

Method for testing an on-chip cache for repair

Memory system with non-volatile data storage unit and method of initializing same

Memory system with non-volatile data storage unit and method of initializing same

Microprocessor memory test circuit and method

Microprocessor memory test circuit and method

Circuit and method for performing tests on memory array cells using external sense amplifier reference current

Circuit and method for performing tests on memory array cells using external sense amplifier reference current

Circuit and method for performing test on memory array cells using external sense amplifier reference current

Circuit and method for performing test on memory array cells using external sense amplifier reference current

Circuit and method for performing tests on memory array cells using external sense amplifier reference current

Circuit and method for performing tests on memory array cells using external sense amplifier reference current


#1,979 Previous [1] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Next




Advertisements  Advertisements