Information Technology

Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask

Global Routing (e.g., Shortest Path, Dead Space, Or Duplicate Trace Elimination)

No:7069532

Access cell design and a method for enabling automatic insertion of access cells into an integrated circuit design

No:7174529

Acute angle avoidance during routing

No:6622294

Adaptive power routing and shield sharing to reduce shield count

No:5808899

Advanced modular cell placement system with cell placement crystallization

No:7152217

Alleviating timing based congestion within circuit designs

No:7058913

Analytical placement method and apparatus

No:6591411

Apparatus and method for determining buffered steiner trees for complex circuits

No:7080341

Apparatus and method for integrated circuit power management

No:6584599

Apparatus and method of layout generation, and program thereof

No:7073154

Apparatus and methods for interconnect zones and associated cells in integrated circuits

No:7346878

Apparatus and methods for providing in-chip microtargets for metrology or inspection

No:6202193

Apparatus for optimization of circuit design

No:5245550

Apparatus for wire routing of vlsi

No:7065729

Approach for routing an integrated circuit

No:5224057

Arrangement method for logic cells in semiconductor ic device

No:7454735

Asic clock floor planning method and structure

No:6496965

Automated design of parallel drive standard cells

No:6510545

Automated shielding algorithm for dynamic circuits

No:7124389

Automated wiring pattern layout method

No:6378121

Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor

No:6253364

Automatic placement and routing device

No:6505334

Automatic placement and routing method, automatic placement and routing apparatus, and semiconductor integrated circuit

No:6330707

Automatic routing method

No:5790414

Automatic routing method and automatic routing apparatus

No:7409669

Automatic test configuration generation facilitating repair of programmable circuits

No:7454736

Automatic trace determination apparatus and computer program thereof

No:7249336

Automatic wiring method for semiconductor integrated circuit, program for the same, and semiconductor integrated circuit

No:7325217

Automatic wiring method for the crosstalk reduction

No:7194719

Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure

No:7376928

Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure

No:6615401

Blocked net buffer insertion

No:7484199

Buffer insertion to reduce wirelength in vlsi circuits

No:6898774

Buffer insertion with adaptive blockage avoidance

No:6883157

Bwb transmission wiring design system

No:6691296

Circuit board design aiding

No:6578184

Circuit design method and circuit design apparatus

No:7451419

Circuit layout device, circuit layout method, and program for execution thereof

No:6976238

Circular vias and interconnect-line ends

No:6601229

Client/server behavioral modeling and testcase development using vhdl for improved logic verification

No:7237216

Clock gating approach to accommodate infrequent additional processing latencies

No:5889682

Clock routing design method using a hieraichical layout design

No:6941532

Clock skew verification methodology for grid-based design

No:7225421

Clock tree distribution generation by determining allowed placement regions for clocked elements

No:7353481

Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit

No:5835378

Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip

No:6622288

Conflict sensitive compaction for resolving phase-shift conflicts in layouts for phase-shifted features

No:6907588

Congestion estimation for register transfer level code

No:5798936

Congestion-driven placement method and computer-implemented integrated-circuit design tool

No:6487706

Contract methodology for concurrent hierarchical design

No:6601222

Coupled noise estimation and avoidance of noise-failure using global routing information